The present invention relates to a pulse generator circuit for outputting a pulse signal of a predetermined pulse width in response to a trigger signal. In particular, the present invention relates to an improvement such that power voltage dependency of a pulse width of a pulse signal is eliminated.
In a semiconductor memory, a pulse signal generated by capturing an address change is employed as a trigger, thereby generating a timing signal of a constant pulse width, and controls the operation of each circuit incorporated in a memory.
FIG. 1 shows a configuration of a conventional pulse generator circuit for generating a pulse signal in response to a trigger signal. This circuit is composed of: the even number of inverters INV1 to INV6 (six inverters in this example) connected in cascade; capacitors C connected respectively between an output node of each inverter at an even-numbered stage excluding the last stage and a ground voltage node and between an output node of each inverter at an odd-numbered stage excluding the first stage and a power voltage node; P-channel transistors TP each having a source-drain path inserted between the power voltage node and the output node of an inverter provided at any even-numbered stage but the last-stage, and each having a gate connected to an output node of the first-stage inverter INV1; and N-channel transistors TN each having a source-drain path inserted between the ground voltage node and an output node of an inverter provided at any odd-numbered stage but the first stage, and each having a gate connected to an input node of a trigger signal.
FIG. 2 is a timing chart showing an example of operation of the pulse generator circuit shown in FIG. 1. In the figure, a trigger signal to be input to the inverter INV1 at the first stage is designated by IN; and signals of the output nodes of the inverters INV1 to INV6 at the first to last stages are designated by V1, V2, V3, V4, V5, and OUT, respectively.
Now, when the signal IN of a pulse width Ta is input, the signals V1, V2, V3, V4, V5, and OUT are initially set to L, H, L, H, L, and H, respectively.
Next, when the signal IN falls into an L level, the signal V1 of the output node of the inverter INV1 at the first stage rises from the initial L level to an H level immediately. Thereafter, a signal V2 of the output node of the inverter INV2 at a next stage starts its falling from the initial H level to the L level. However, a capacitor C is connected to its output node, and thus, its falling is gentle.
When the signal V2 becomes lower than a circuit threshold voltage of the inverter INV3 at a next stage at a time Tb, the signal V3 of the output node of this inverter INV3 starts its rising from the initial L level toward the H level. In this case also, the capacitor C is connected to its output node, and thus, its rising is gentle.
When the signal V3 becomes higher than a circuit threshold voltage of the inverter INV4 at a next stage at a time Tc, the signal V4 of the output node of this inverter INV4 starts its falling from the initial H level toward the L level. In this case also, its output node is connected to the capacitor C, and thus, its falling is gentle.
When the signal V4 becomes lower than a circuit threshold voltage of the inverter INV5 at a next stage, the signal V5 of the output node of this inverter INV5 starts its rising from the initial L level toward the H level. In this case also, the capacitor is connected to the output node of the inverter INV5, and thus, its rising is gentle.
When the signal V5 becomes higher than a circuit threshold voltage of the inverter INV6 at the last stage, the signal OUT of the output node of this inverter INV6 falls from the initial H level to the L level immediately.
That is, this pulse generator circuit outputs the signal OUT having a predetermined pulse width when a signal IN being a trigger signal is input. The pulse width of the output signal OUT is determined according to: a value of the capacitor C connected to each of the output nodes of the inverters INV2 to INV5; an element size of P-channel transistor and N-channel transistor constituting each inverter for charging and discharging the respective output nodes (N-channel transistors for the inverters INV2 and INV4 and P-channel transistors for the inverters INV3 and INV5); and a circuit threshold voltage of each inverter, in particular, a circuit threshold voltage of the inverters INV3 to INV6.
In the meantime, in the conventional circuit shown in FIG. 1, a circuit threshold voltage of each inverter or the current driving capacity of the P-channel and N-channel transistors which constitute each inverter varies depending on the value of the power voltage supplied to each inverter. Thus, the pulse width of the output signal OUT has power voltage dependency. For example, when the power voltage is shifted to be higher, the pulse width of the output signal OUT becomes shorter. Conversely, when the voltage is shifted to be lower, the pulse width becomes longer.
Also, assuming that such a pulse generator circuit is provided in a semiconductor memory to control operation of an internal circuit, in a state where a circuit, for example, an equalizing circuit or a latch circuit, is set to be prevented from malfunctioning even when a power voltage is high and a pulse width is short taking in consideration a power voltage dependency of a pulse width of a pulse signal generated at a pulse generating circuit, a pulse width of a pulse signal for controlling operation of the equalizing circuit or the latch circuit becomes long when the power voltage is lowered and the pulse width becomes longer. Thereby, such a problem as increased power consumption or the like will occur in a case that an access time is delayed or a power is lowered.